In a semiconductor memory device such as a dynamic RAM (random access memory), the transmission a data signal can shift of an effective voltage potential of the data signal. In a dynamic RAM including CMOS transistors, a voltage drop about equal to the threshold voltage of the MOS transistor occurs when transmitting a signal through the MOS transistor. This inevitable voltage drop becomes an obstacle to the accurate reading or writing of data and potentially could cause the loss of data. To solve this problem, a voltage boosting circuit can raise a voltage level to compensate for a voltage drop. U.S. Pat. No. 5,610,549 entitled "VOLTAGE BOOSTING CIRCUIT OF A SEMICONDUCTOR MEMORY CIRCUIT", and U.S. Pat. No. 5,521,546 entitled "VOLTAGE BOOSTING CIRCUIT CONSTRUCTED ON AN INTEGRATED CIRCUIT SUBSTRATE, AS FOR A SEMICONDUCTOR MEMORY DEVICE" describe known voltage boosting circuits and are hereby incorporated by reference in their entirety.
FIG. 1 is a block diagram of a known dynamic RAM device 10 that includes eight banks (or cell array banks). Although not shown in FIG. 1, each bank 12 includes circuits for selecting rows and columns (for example, a row decoder circuit and a column decoder circuit), a sense amplifier circuit, a column pass gate circuit, and a data input/output buffer circuit. Each bank 12 also has a respective voltage boosting circuit 14 having a structure such as those disclosed in U.S. Pat. No. 5,610,549 or 5,521,546 patent. Banks 12 connect to a common line L1. When banks 12 are selected (or activated), the corresponding voltage boosting circuits 14 supply the selected banks 12 with a high voltage Vpp (having a voltage level higher than a power supply voltage level). An active signal BANKi indicates the activation of the bank i.
Dynamic RAM devices having larger storage capacity tend to have more banks. In the dynamic RAM devices having a multi-bank structure, circuitry required for voltage boosting circuits 14, which are selected in accordance with activation information for the respective banks 12, increases the required chip area. As a result, chip efficiency (an occupied area by the banks of a chip area) is lowered because the number of voltage boosting circuits 14 corresponds to the number of banks 12.